Ultra-low power Chip Design of a Passive UHF RFID Tag

Speaker: Bram De Muer (IC Sense) & Ramses Valvekens (Easics)

Company/ Institute: IC Sense & Easics

Event: 1st work meeting

Date: 27 May 2009


EPCglobal Gen-2 provides a standard for versatile passive RFID tags. We will discuss the design of the TegoTag(TM), developed for Tego, a Boston-based RFID company.
This chip incorporates the vision of “active functionality in a passive tag”. It harvests all its energy from the incoming 900 MHz waves of a RFID reader device (located at a distance of up to multiple meters), and does not require a battery. Besides 32 Kilobytes of on-chip non-volatile memory (2500 times more than competing tags), the chip supports external interfacing with sensors and actuators. All aspects of the design are driven by state-of-the-art ultra-low-power techniques. First of all, as much power as possible is harvested from the air and secondly every part of the chip is put on a stringent and dynamically regulated power budget. Transmission is done using backscattering.
After a short introduction on RFID standards, Ramses and Bram will discuss the chip’s architecture, digital/analog partitioning, power management, RF-DC rectification, memory -access and -management, receive- and transmit-datapaths, the EPC command processor, and interfacing to the environment.

Slides: click here to download (Community members only, login required)

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